K60P100M100SF2RM Datasheet, PDF (1530/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
51.4.2 Receiver
SBR12:0
BRFA4:0
MODULE
CLOCK
RE
RAF
BAUDRATE
GENERATOR
RECEIVE
CONTROL
RxD
LOOPS
RSRC
RECEIVER
SOURCE
CONTROL
From Transmitter
RxD
ACTIVE EDGE
DETECT
INTERNAL BUS
DATA BUFFER
VARIABLE 12-BIT RECEIVE
SHIFT REGISTER
SHIFT DIRECTION
M
M10
LBKDE
MSBF
RXINV
PE
PARITY
WAKEUP
PT
LOGIC
LOGIC
IRQ / DMA
LOGIC
DMA Requests
IRQ Requests
INFRARED LOGIC
7816 LOGIC
Figure 51-189. UART receiver block diagram
To TxD
51.4.2.1 Receiver character length
The UART receiver can accommodate 8-, 9-, or 10-bit data characters. The states of the
C1[M] and C1[PE] bits and the C4[M10] bit determine the length of data characters.
When receiving 9 or 10-bit data, bit C3[R8] is the ninth bit (bit 8).
51.4.2.2 Receiver bit ordering
When the S2[MSBF] bit is set, the receiver operates such that the first bit received after
the start bit is the MSB of the data word. Likewise the bit received immediately
preceding the parity bit (or the stop bit if parity is not enabled) is treated as the LSB for
1530
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.