K60P100M100SF2RM Datasheet, PDF (950/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map and Register Definition
39.3.10 Features Mode Selection (FTMx_MODE)
This register contains the control bits used to configure the fault interrupt and fault
control, capture test mode, PWM synchronization, write protection, channel output
initialization, and enable the enhanced features of the FTM. These controls relate to all
channels within this module.
Addresses: FTM0_MODE is 4003_8000h base + 54h offset = 4003_8054h
FTM1_MODE is 4003_9000h base + 54h offset = 4003_9054h
FTM2_MODE is 400B_8000h base + 54h offset = 400B_8054h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
W
FAULTM
Reset 0
Field
31–8
Reserved
7
FAULTIE
6–5
FAULTM
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
FTMx_MODE field descriptions
Description
This read-only field is reserved and always has the value zero.
Fault Interrupt Enable
Enables the generation of an interrupt when a fault is detected by FTM and the FTM fault control is
enabled.
0 Fault control interrupt is disabled.
1 Fault control interrupt is enabled.
Fault Control Mode
Defines the FTM fault control mode.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
00 Fault control is disabled for all channels.
01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is
the manual fault clearing.
10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
950
Freescale Semiconductor, Inc.