K60P100M100SF2RM Datasheet, PDF (321/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
0
JTAG
MC_SRSH field descriptions (continued)
Chapter 13 Mode Controller
Description
Indicates reset was caused by the ARM core indication of a LOCKUP event.
0 Reset not caused by core LOCKUP event
1 Reset caused by core LOCKUP event
JTAG generated reset
Indicates reset was caused by JTAG selection of certain IR codes (EZPORT, EXTEST, HIGHZ, and
CLAMP).
0 Reset not caused by JTAG
1 Reset caused by JTAG
13.2.2 System Reset Status Register Low (MC_SRSL)
The SRSH:SRSL registers includes read-only status flags to indicate the source of the
most recent reset. The reset state of these bits depends on what caused the MCU to reset.
Throughout this document, SRS refers to SRSH:SRSL.
NOTE
The reset value of this register depends on the reset type:
• POR — 0x82
• LVD — 0x02
• Low-leakage wake-up due to RESET pin assertion — 0x41
• Low-leakage wake-up due to other wake-up sources —
0x01
• Other reset — bits 6-5 and 2 are set if their corresponding
reset source caused the reset
Address: MC_SRSL is 4007_E000h base + 1h offset = 4007_E001h
Bit
7
6
5
Read POR
PIN
COP
Write
Reset
1
0
0
4
3
0
0
0
2
LOC
0
1
LVD
0
WAKEUP
1
0
MC_SRSL field descriptions
Field
7
POR
Power-on reset
Description
Indicates a reset was caused by the power-on detection logic. Because the internal supply voltage was
ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred
while the internal supply was below the LVD threshold.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
321