K60P100M100SF2RM Datasheet, PDF (709/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 29 External Bus Interface (FlexBus)
Byte Select
External
Data Bus
FB_BE_31_24 FB_BE_23_16 FB_BE_15_8
FB_D[31:24] FB_D[23:16] FB_D[15:8]
FB_BE_7_0
FB_D[7:0]
32-Bit Port
Memory
Byte 3
Byte 2
Byte 1
Byte 0
16-Bit Port
Memory
Byte 1
Byte 3
Byte 0
Byte 2
Driven with
address values
8-Bit Port
Memory
Byte 0
Byte 1
Byte 2
Byte 3
Driven with
address values
Figure 29-23. Connections for External Memory Port Sizes (CSCRn[BLS] = 0)
The following figure shows the byte lanes that external memory connects to and the
sequential transfers of a 32-bit transfer for the supported port sizes when byte lane shift is
enabled.
Byte Select
External
Data Bus
FB_BE_7_0 FB_BE_15_8 FB_BE_23_16 FB_BE_31_24
FB_D[31:24] FB_D[23:16] FB_D[15:8] FB_D[7:0]
32-Bit Port
Memory
16-Bit Port
Memory
Byte 3
Byte 2
Driven with
address values
Byte 1
Byte 1
Byte 3
Byte 0
Byte 0
Byte 2
8-Bit Port
Memory
Driven with
address values
Byte 0
Byte 1
Byte 2
Byte 3
Figure 29-24. Connections for External Memory Port Sizes (CSCRn[BLS] = 1)
29.4.4 Address/Data Bus Multiplexing
The interface supports a single 32-bit wide multiplexed address and data bus
(FB_AD[31:0]). The full 32-bit address is always driven on the first clock of a bus cycle.
During the data phase, the FB_AD[31:0] lines used for data are determined by the
programmed port size for the corresponding chip select. The device continues to drive the
address on any FB_AD[31:0] lines not used for data.
The tables below lists the supported combinations of address and data bus widths for each
CSCRn[BLS] setting.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
709