K60P100M100SF2RM Datasheet, PDF (1598/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
SDHC_IRQSTAT field descriptions (continued)
Field
21
DCE
0b No Error
1b Error
Data CRC Error
Description
Occurs when detecting a CRC error when transferring read data, which uses the DAT line, or when
detecting the Write CRC status having a value other than 010.
20
DTOE
0b No Error
1b Error
Data Timeout Error
Occurs when detecting one of following time-out conditions.
• Busy time-out for R1b,R5b type
• Busy time-out after Write CRC status
• Read Data time-out
0b No Error
1b Time out
19
Command Index Error
CIE
Occurs if a Command Index error occurs in the command response.
18
CEBE
0b No Error
1b Error
Command End Bit Error
Occurs when detecting that the end bit of a command response is 0.
17
CCE
0b No Error
1b End Bit Error Generated
Command CRC Error
Command CRC Error is generated in two cases.
• If a response is returned and the Command Timeout Error is set to 0 (indicating no time-out), this bit
is set when detecting a CRC error in the command response.
• The SDHC detects a CMD line conflict by monitoring the CMD line when a command is issued. If
the SDHC drives the CMD line to 1, but detects 0 on the CMD line at the next SDCLK edge, then
the SDHC shall abort the command (Stop driving CMD line) and set this bit to 1. The Command
Timeout Error shall also be set to 1 to distinguish CMD line conflict.
16
CTOE
0b No Error
1b CRC Error Generated
Command Timeout Error
Occurs only if no response is returned within 64 SDCLK cycles from the end bit of the command. If the
SDHC detects a CMD line conflict, in which case a Command CRC Error shall also be set, this bit shall be
set without waiting for 64 SDCLK cycles. This is because the command will be aborted by the SDHC.
0b No Error
1b Time out
Table continues on the next page...
1598
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.