K60P100M100SF2RM Datasheet, PDF (840/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
for the different configurations. For best calibration results, it is recommended to set
hardware averaging to maximum (AVGE=1, AVGS=11 for average of 32), ADC clock
frequency f_ADCK less than or equal to 4 MHz, V_REFH=V_DDA, and to calibrate at nominal
voltage and temperature. The input channel, conversion mode continuous function,
compare function, resolution mode, and differential/single-ended mode are all ignored
during the calibration function.
To initiate calibration, the user sets the CAL bit and the calibration will automatically
begin if the ADTRG bit is 0. If ADTRG is 1, the CAL bit will not get set and the
calibration fail flag (CALF) will be set. While calibration is active, no ADC register can
be written and no stop mode may be entered, or the calibration routine will be aborted
causing the CAL bit to clear and the CALF bit to set. At the end of a calibration
sequence, the COCO bit of the SC1A register will be set. The AIEN bit can be used to
allow an interrupt to occur at the end of a calibration sequence. At the end of the
calibration routine, if the CALF bit is not set, the automatic calibration routine completed
successfully.
To complete calibration, the user must generate the gain calibration values using the
following procedure:
1. Initialize (clear) a 16-bit variable in RAM.
2. Add the plus-side calibration results CLP0, CLP1, CLP2, CLP3, CLP4, and CLPS to
the variable.
3. Divide the variable by two.
4. Set the MSB of the variable.
5. The previous two steps can be achieved by setting the carry bit, rotating to the right
through the carry bit on the high byte and again on the low byte.
6. Store the value in the plus-side gain calibration register (PG).
7. Repeat the procedure for the minus-side gain calibration value.
When calibration is complete, the user may reconfigure and use the ADC as desired. A
second calibration may also be performed if desired by clearing and again setting the
CAL bit.
Overall, the calibration routine may take as many as 14k ADCK cycles and 100 bus
cycles, depending on the results and the clock source chosen. For an 8 MHz clock source,
this length amounts to about 1.7 ms. To reduce this latency, the calibration values (offset,
plus-side and minus-side gain, and plus-side and minus-side calibration values) may be
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
840
Freescale Semiconductor, Inc.