K60P100M100SF2RM Datasheet, PDF (1078/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
LPTMRx_PSR field descriptions (continued)
Field
6–3
PRESCALE
Prescale Value
Description
The Prescaler Value register field configures the size of the Prescaler (in Time Counter mode) or width of
the Glitch Filter (in Pulse Counter mode). The Prescale Value should only be altered when the LPTMR is
disabled.
2
PBYP
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Prescaler divides the prescaler clock by 2; Glitch Filter does not support this configuration.
Prescaler divides the prescaler clock by 4; Glitch Filter recognizes change on input pin after 2
rising clock edges.
Prescaler divides the prescaler clock by 8; Glitch Filter recognizes change on input pin after 4
rising clock edges.
Prescaler divides the prescaler clock by 16; Glitch Filter recognizes change on input pin after 8
rising clock edges.
Prescaler divides the prescaler clock by 32; Glitch Filter recognizes change on input pin after 16
rising clock edges.
Prescaler divides the prescaler clock by 64; Glitch Filter recognizes change on input pin after 32
rising clock edges.
Prescaler divides the prescaler clock by 128; Glitch Filter recognizes change on input pin after 64
rising clock edges.
Prescaler divides the prescaler clock by 256; Glitch Filter recognizes change on input pin after 128
rising clock edges.
Prescaler divides the prescaler clock by 512; Glitch Filter recognizes change on input pin after 256
rising clock edges.
Prescaler divides the prescaler clock by 1024; Glitch Filter recognizes change on input pin after
512 rising clock edges.
Prescaler divides the prescaler clock by 2048; Glitch Filter recognizes change on input pin after
1024 rising clock edges.
Prescaler divides the prescaler clock by 4096; Glitch Filter recognizes change on input pin after
2048 rising clock edges.
Prescaler divides the prescaler clock by 8192; Glitch Filter recognizes change on input pin after
4096 rising clock edges.
Prescaler divides the prescaler clock by 16384; Glitch Filter recognizes change on input pin after
8192 rising clock edges.
Prescaler divides the prescaler clock by 32768; Glitch Filter recognizes change on input pin after
16384 rising clock edges.
Prescaler divides the prescaler clock by 65536; Glitch Filter recognizes change on input pin after
32768 rising clock edges.
Prescaler Bypass
When the Prescaler Bypass is set the selected prescaler clock (in Time Counter mode) or selected input
source (in Pulse Counter mode) directly clocks the LPTMR Counter Register. When the Prescaler Bypass
is clear, the LPTMR Counter Register is clocked by the output of the prescaler/glitch filter. The Prescaler
Bypass should only be altered when the LPTMR is disabled.
1–0
PCS
0 Prescaler/Glitch Filter is enabled.
1 Prescaler/Glitch Filter is bypassed.
Prescaler Clock Select
The Prescaler Clock Select selects the clock to be used by the LPTMR prescaler/glitch filter. The
Prescaler Clock Select should only be altered when the LPTMR is disabled. The clock connections vary
by device. See the Chip Configuration details for information on the connections to these inputs.
Table continues on the next page...
1078
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.