K60P100M100SF2RM Datasheet, PDF (1557/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 51 Universal Asynchronous Receiver/Transmitter (UART)
51.6.1.3 Exit from low-power modes
The receive input active edge detect circuit is still active on low power modes (wait and
stop). An active edge on the receive input brings the CPU out of low power mode if the
interrupt is not masked (S2[RXEDGIF]=1).
51.7 DMA operation
In the transmitter, flags S1[TDRE] can be configured to assert a DMA transfer request. In
the receiver, flag S1[RDRF], can be configured to assert a DMA transfer request. The
following table shows the configuration bit settings required to configure each flag for
DMA operation.
Table 51-207. DMA configuration
Flag
TDRE
RDRF
Request enable bit
TIE = 1
RIE = 1
DMA select bit
TDMAS = 1
RDMAS = 1
When a flag is configured for a DMA request, its associated DMA request is asserted
when the flag is set. When the S1[RDRF] flag is configured as a DMA request, the
clearing mechanism of reading S1 register followed by reading D register does not clear
the associated flag. The DMA request remains asserted until an indication is received that
the DMA transactions are done. When this indication is received, the flag bit and the
associated DMA request are cleared. If the DMA operation failed to remove the situation
that caused the DMA request another request will be issued.
51.8 Application information
This section describes the UART application information.
51.8.1 Transmit/receive data buffer operation
The UART has independent receive and transmit buffers. The size of these buffers may
vary depending on the implementation of the module. The implemented size of the
buffers is a fixed constant via the PFIFO[TXFIFOSIZE] and PFIFO[RXFIFOSIZE]
fields. Additionally, legacy support is provided that allows for the FIFO structure to
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1557