K60P100M100SF2RM Datasheet, PDF (1506/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and registers
Addresses: UART0_MODEM is 4006_A000h base + Dh offset = 4006_A00Dh
UART1_MODEM is 4006_B000h base + Dh offset = 4006_B00Dh
UART2_MODEM is 4006_C000h base + Dh offset = 4006_C00Dh
UART3_MODEM is 4006_D000h base + Dh offset = 4006_D00Dh
UART4_MODEM is 400E_A000h base + Dh offset = 400E_A00Dh
Bit
7
Read
Write
Reset
0
6
5
0
0
0
4
3
2
1
0
RXRTSE TXRTSPOL TXRTSE TXCTSE
0
0
0
0
0
UARTx_MODEM field descriptions
Field
7–4
Reserved
3
RXRTSE
Description
This read-only field is reserved and always has the value zero.
Receiver request-to-send enable
Allows the RTS output to control the CTS input of the transmitting device to prevent receiver overrun.
NOTE: Do not set both RXRTSE and TXRTSE.
2
TXRTSPOL
0 The receiver has no effect on RTS.
1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or
greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver
data register (FIFO) is less than RWFIFO[RXWATER].
Transmitter request-to-send polarity
Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the polarity of the receiver RTS.
RTS will remain negated in the active low state unless TXRTSE is set.
1
TXRTSE
0 Transmitter RTS is active low.
1 Transmitter RTS is active high.
Transmitter request-to-send enable
Controls RTS before and after a transmission.
0
TXCTSE
0 The transmitter has no effect on RTS.
1 When a character is placed into an empty transmitter data buffer(FIFO), RTS asserts one bit time
before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter
data buffer(FIFO) and shift register are completely sent, including the last stop bit.
Transmitter clear-to-send enable
TXCTSE controls the operation of the transmitter. TXCTSE can be set independently from the state of
TXRTSE and RXRTSE.
0 CTS has no effect on the transmitter.
1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send
a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in
the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is
being sent do not affect its transmission.
1506
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.