K60P100M100SF2RM Datasheet, PDF (1334/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
CANx_IMASK2 field descriptions (continued)
Field
Description
0 The corresponding buffer Interrupt is disabled.
1 The corresponding buffer Interrupt is enabled.
48.3.11 Interrupt Masks 1 Register (CANx_IMASK1)
This register allows any number of a range of 32 Message Buffer Interrupts to be enabled
or disabled. It contains one interrupt mask bit per buffer, enabling the CPU to determine
which buffer generates an interrupt after a successful transmission or reception (i.e. when
the corresponding IFLAG1 bit is set).
Addresses: CAN0_IMASK1 is 4002_4000h base + 28h offset = 4002_4028h
CAN1_IMASK1 is 400A_4000h base + 28h offset = 400A_4028h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BUFLM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CANx_IMASK1 field descriptions
Field
31–0
BUFLM
Description
Buffer MB_i Mask
Each bit enables or disables the corresponding FlexCAN Message Buffer Interrupt.
NOTE: Setting or clearing a bit in the IMASK1 Register can assert or negate an interrupt request, if the
corresponding IFLAG1 bit is set.
0 The corresponding buffer Interrupt is disabled.
1 The corresponding buffer Interrupt is enabled.
48.3.12 Interrupt Flags 2 Register (CANx_IFLAG2)
This register defines the flags for 32 Message Buffer interrupts. It contains one interrupt
flag bit per buffer. Each successful transmission or reception sets the corresponding
IFLAG2 bit. If the corresponding IMASK2 bit is set, an interrupt will be generated. The
interrupt flag must be cleared by writing 1 to it. Writing 0 has no effect.
Before updating MCR[MAXMB] field, CPU must service the IFLAG2 bits whose MB
value is greater than the MCR[MAXMB] to be updated; otherwise, they will remain set
and be inconsistent with the amount of MBs available.
1334
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.