K60P100M100SF2RM Datasheet, PDF (373/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Master-to-slave
transfer
MGPCR[AULB]
No arbitration
1
2
Arbitration allowed
3
4
5
Lost control
Chapter 17 Crossbar Switch (AXBS)
No arbitration
6
7
8
9
Lost control
10
No arbitration
11
12
1 beat 1 beat
12 beat burst
Figure 17-28. Undefined length burst example
In this example, a master runs an undefined length burst and the MGPCR[AULB] bits
indicate arbitration occurs after the fourth beat of the burst. The master runs two
sequential beats and then starts what will be a 12-beat undefined length burst access to a
new address within the same slave port region as the previous access. The crossbar does
not allow an arbitration point until the fourth overall access, or the second beat of the
second burst. At that point, all remaining accesses are open for arbitration until the master
loses control of the slave port.
Assume the master loses control of the slave port after the fifth beat of the second burst.
After the master regains control of the slave port no arbitration point is available until
after the master has run four more beats of its burst. After the fourth beat of the now
continued burst, or the ninth beat of the second burst from the master's perspective, is
taken, all beats of the burst are once again open for arbitration until the master loses
control of the slave port.
Assume the master again loses control of the slave port on the fifth beat of the third now
continued burst, or the 10th beat of the second burst from the master's perspective. After
the master regains control of the slave port, it is allowed to complete its final two beats of
its burst without facing arbitration.
Note
Fixed-length burst accesses are not affected by the AULB bits.
All fixed-length burst accesses lock out arbitration until the last
beat of the fixed-length burst.
17.3.3.2 Fixed-priority operation
When operating in Fixed-Priority mode, each master is assigned a unique priority level in
the priority registers (PRSn) . If two masters request access to a slave port, the master
with the highest priority in the selected priority register gains control over the slave port.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
373