K60P100M100SF2RM Datasheet, PDF (1463/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

ICR
(hex)
19
1A
1B
1C
1D
1E
1F
Chapter 50 Inter-Integrated Circuit (I2C)
Table 50-41. I2C Divider and Hold Values (continued)
SCL
Divider
96
112
128
144
160
192
240
SDA Hold SCL Hold SCL Hold
Value
(Start)
(Stop)
Value
Value
9
46
49
17
54
57
17
62
65
25
70
73
25
78
81
33
94
97
33
118
121
ICR
(hex)
39
3A
3B
3C
3D
3E
3F
SCL
Divider
(clocks)
1536
1792
2048
2304
2560
3072
3840
SDA Hold SCL Hold SCL Hold
(clocks) (Start)
(Stop)
Value
Value
129
766
769
257
894
897
257
1022
1025
385
1150
1153
385
1278
1281
513
1534
1537
513
1918
1921
50.4.2 10-bit Address
For 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte.
Various combinations of read/write formats are possible within a transfer that includes
10-bit addressing.
50.4.2.1 Master-Transmitter Addresses a Slave-Receiver
The transfer direction is not changed. When a 10-bit address follows a START condition,
each slave compares the first seven bits of the first byte of the slave address (11110XX)
with its own address and tests whether the eighth bit (R/W direction bit) is 0. It is
possible that more than one device finds a match and generates an acknowledge (A1).
Each slave that finds a match compares the eight bits of the second byte of the slave
address with its own address, but only one slave finds a match and generate an
acknowledge (A2). The matching slave remains addressed by the master until it receives
a STOP condition (P) or a repeated START condition (Sr) followed by a different slave
address.
Table 50-42. Master-Transmitter Addresses Slave-Receiver with a 10-bit
Address
S
Slave R/W
A1 Slave
A2
Data
A
addres 0
addres
s first 7
s
bits
second
11110
byte
+
AD[8:1]
AD10
+ AD9
...
Data
A/A
P
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1463