K60P100M100SF2RM Datasheet, PDF (117/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Peripheral bus
controller 0
Register
access
Chapter 3 Chip Configuration
Transfers
Other peripherals
16-bit SAR ADC
Module signals
Figure 3-36. 16-bit SAR ADC with PGA configuration
Table 3-46. Reference links to related information
Topic
Full description
System memory map
Clocking
Power management
Signal multiplexing
Related module
16-bit SAR ADC with
PGA
Port control
Reference
16-bit SAR ADC with PGA
System memory map
Clock distribution
Power management
Signal multiplexing
3.7.1.1 ADC instantiation information
This device contains two ADCs. Each ADC contains a PGA channel for a total of two
separate PGAs.
3.7.1.1.1 Number of ADC channels
The number of ADC channels present on the device is determined by the pinout of the
specific device package. For details regarding the number of ADC channel available on a
particular package, refer to the signal multiplexing chapter of this MCU.
3.7.1.2 DMA Support on ADC
Applications may require continuous sampling of the ADC (4K samples/sec) that may
have considerable load on the CPU. Though using PDB to trigger ADC may reduce some
CPU load, The ADC supports DMA request functionality for higher performance when
the ADC is sampled at a very high rate or cases were PDB is bypassed. The ADC can
trigger the DMA (via DMA req) on conversion completion.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
117