K60P100M100SF2RM Datasheet, PDF (311/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

• RUNM set to 10b to enter VLPR.
• Flash programming/erasing is not allowed.
• The slow IRC must not be enabled.
• All clock monitors must be disabled before entering VLPR.
Chapter 13 Mode Controller
While in VLPR, the regulator is slow responding and cannot handle fast load transitions.
Therefore, do not change the clock frequency. This includes a requirement to not modify
the module clock enables in the SIM or any clock divider registers.
To re-enter normal run mode, simply clear RUNM. The REGONS and VLPRS bits in the
REGSC register are read-only status bits that indicate if the regulator is in run regulation
mode or not:
• When REGONS is set, the regulator is in run regulation mode and the MCU can run
at full speed in any clock mode. If a higher execution frequency is desired, poll
REGONS until it is set when returning from VLPR.
• When VLPRS is set, the system is fully in VLPR mode.
NOTE
• Do not enter VLPS, LLS, or VLLSx until the transition to
VLPR completes as indicated by the VLPRS bit.
• Do not attempt to transition out of run mode until the
REGONS bit sets.
VLPR also provides the option to return to run regulation if any interrupt occurs. This is
done by setting the low power wake up on interrupt (LPWUI) bit in the PMCTRL
register. In the interrupt service routine (ISR) it is not be necessary to poll the REGONS
before increasing the frequency. The VLPR frequency limits are such that the regulator is
in run regulation and REGONS is set before the ISR is entered.
Any reset exits VLPR, clears RUNM, REGONS is set, and the device is in normal run
mode after the CPU exits its reset flow.
13.1.2.3 Wait Modes
This device contains two different wait modes:
• Wait
• Very low power wait
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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