K60P100M100SF2RM Datasheet, PDF (1318/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
CANx_MCR field descriptions (continued)
Field
Description
Therefore the software can poll the FRZACK bit to know when FlexCAN has actually entered Freeze
Mode. If Freeze Mode request is negated, then this bit is negated once the FlexCAN prescaler is running
again. If Freeze Mode is requested while FlexCAN is in a low power mode, then the FRZACK bit will only
be set when the low power mode is exited. See Section "Freeze Mode".
NOTE: FRZACK will be asserted within 178 CAN bits from the freeze mode request by the CPU, and
negated within 2 CAN bits after the freeze mode request removal (see Section "Protocol
Timing").
23
SUPV
0 FlexCAN not in Freeze Mode, prescaler running
1 FlexCAN in Freeze Mode, prescaler stopped
Supervisor Mode
This bit configures the FlexCAN to be either in Supervisor or User Mode. The registers affected by this bit
are marked as S/U in the Access Type column of the module memory map. Reset value of this bit is ‘1’,
so the affected registers start with Supervisor access allowance only. This bit can only be written in
Freeze mode as it is blocked by hardware in other modes.
22
SLFWAK
0 FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses.
1 FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access
behaves as though the access was done to an unimplemented register location.
Self Wake Up
This bit enables the Self Wake Up feature when FlexCAN is in a low power mode other than Disable
Mode. When this feature is enabled, the FlexCAN module monitors the bus for wake up event, that is, a
recessive-to-dominant transition.
If a wake up event is detected during Doze Mode, FlexCAN requests to resume its clocks and, if enabled
to do so, generates a Wake Up interrupt to the CPU.
If a wake up event is detected during Stop Mode, then FlexCAN generates, if enabled to do so, a Wake
Up interrupt to the CPU so that it can exit Stop Mode globally and FlexCAN can request to resume the
clocks.
When FlexCAN is in a low power mode other than Disable Mode, this bit cannot be written as it is blocked
by hardware.
21
WRNEN
0 FlexCAN Self Wake Up feature is disabled.
1 FlexCAN Self Wake Up feature is enabled.
Warning Interrupt Enable
When asserted, this bit enables the generation of the TWRNINT and RWRNINT flags in the Error and
Status Register. If WRNEN is negated, the TWRNINT and RWRNINT flags will always be zero,
independent of the values of the error counters, and no warning interrupt will ever be generated. This bit
can only be written in Freeze mode as it is blocked by hardware in other modes.
20
LPMACK
0 TWRNINT and RWRNINT bits are zero, independent of the values in the error counters.
1 TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96
to greater than or equal to 96.
Low Power Mode Acknowledge
This read-only bit indicates that FlexCAN is in a low power mode (Disable Mode, Doze Mode, Stop
Mode). A low power mode can not be entered until all current transmission or reception processes have
finished, so the CPU can poll the LPMACK bit to know when FlexCAN has actually entered low power
mode.
Table continues on the next page...
1318
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.