K60P100M100SF2RM Datasheet, PDF (611/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 27 Flash Memory Controller (FMC)
27.4.10 Cache Data Storage (upper word) (FMC_DATAW1SU)
The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are
numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x
denotes the way, y denotes the set, and U and L represent upper and lower word,
respectively. This section represents data for the upper word (bits [63:32]) of all 8 sets
(n=0-7) in way 1.
Addresses: FMC_DATAW1S0U is 4001_F000h base + 240h offset = 4001_F240h
FMC_DATAW1S1U is 4001_F000h base + 248h offset = 4001_F248h
FMC_DATAW1S2U is 4001_F000h base + 250h offset = 4001_F250h
FMC_DATAW1S3U is 4001_F000h base + 258h offset = 4001_F258h
FMC_DATAW1S4U is 4001_F000h base + 260h offset = 4001_F260h
FMC_DATAW1S5U is 4001_F000h base + 268h offset = 4001_F268h
FMC_DATAW1S6U is 4001_F000h base + 270h offset = 4001_F270h
FMC_DATAW1S7U is 4001_F000h base + 278h offset = 4001_F278h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
data[63:32]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FMC_DATAW1SnU field descriptions
Field
31–0
data[63:32]
Bits [63:32] of data entry
Description
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
611