K60P100M100SF2RM Datasheet, PDF (48/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Section Number
Title
Page
50.3.6 I2C Control Register 2 (I2Cx_C2)...............................................................................................................1453
50.3.7 I2C Programmable Input Glitch Filter register (I2Cx_FLT).......................................................................1454
50.3.8 I2C Range Address register (I2Cx_RA)......................................................................................................1454
50.3.9 I2C SMBus Control and Status register (I2Cx_SMB).................................................................................1455
50.3.10 I2C Address Register 2 (I2Cx_A2)..............................................................................................................1456
50.3.11 I2C SCL Low Timeout Register High (I2Cx_SLTH)..................................................................................1457
50.3.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL)...................................................................................1457
50.4 Functional Description..................................................................................................................................................1458
50.4.1 I2C Protocol.................................................................................................................................................1458
50.4.2 10-bit Address..............................................................................................................................................1463
50.4.3 Address Matching........................................................................................................................................1464
50.4.4 System Management Bus Specification.......................................................................................................1465
50.4.5 Resets...........................................................................................................................................................1468
50.4.6 Interrupts......................................................................................................................................................1468
50.4.7 Programmable Input Glitch Filter................................................................................................................1470
50.4.8 Address Matching Wakeup..........................................................................................................................1470
50.4.9 DMA Support...............................................................................................................................................1471
50.5 Initialization/Application Information..........................................................................................................................1471
Chapter 51
Universal Asynchronous Receiver/Transmitter (UART)
51.1 Introduction...................................................................................................................................................................1475
51.1.1 Features........................................................................................................................................................1475
51.1.2 Modes of operation......................................................................................................................................1477
51.2 UART signal descriptions.............................................................................................................................................1478
51.2.1 Detailed signal descriptions.........................................................................................................................1478
51.3 Memory map and registers............................................................................................................................................1479
51.3.1 UART Baud Rate Registers:High (UARTx_BDH).....................................................................................1487
51.3.2 UART Baud Rate Registers: Low (UARTx_BDL).....................................................................................1489
51.3.3 UART Control Register 1 (UARTx_C1).....................................................................................................1490
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
48
Freescale Semiconductor, Inc.