K60P100M100SF2RM Datasheet, PDF (1690/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map/register definition
I2Sx_CR field descriptions (continued)
Field
Description
This bit is used to enable/disable the I²S. When disabled, all I²S status bits are preset to the same state
produced by the power-on reset, all control bits are unaffected, the contents of Tx and Rx FIFOs are
cleared. When I²S is disabled, all internal clocks are disabled (except register access clock).
0 I²S is disabled.
1 I²S is enabled.
53.3.6 I²S Interrupt Status Register (I2Sx_ISR)
The I2S interrupt status register (ISR) is used to monitor the I2S. This register is used by
the core to interrogate the status of the I2S. In gated mode of operation the TFS, RFS,
TLS, RLS, TFRC and RFRC bits of AISR register are not generated. The status bits are
described in the following table.
NOTE
• I²S status flags are valid when I²S is enabled.
• All the flags in the ISR are updated after the first bit of the
next I²S word has completed transmission or reception.
Certain status bits (ROE0/1 and TUE0/1) are cleared by
writing 1 to the corresponding interrupt status bit in ISR.
Addresses: I2S0_ISR is 4002_F000h base + 14h offset = 4002_F014h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
RXT
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
TFS RFS TLS RLS
W
w1c w1c w1c w1c
Reset 0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1690
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.