K60P100M100SF2RM Datasheet, PDF (1405/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
17–16
PBR
15–12
CSSCK
SPIx_CTARn field descriptions (continued)
Chapter 49 SPI (DSPI)
Description
Selects the prescaler value for the delay between the negation of the PCS signal at the end of a frame
and the assertion of PCS at the beginning of the next frame. The PDT field is only used in master mode.
See the DT field description for details on how to compute the Delay after Transfer. Refer Delay after
Transfer (t_DT) for more details.
00 Delay after Transfer Prescaler value is 1.
01 Delay after Transfer Prescaler value is 3.
10 Delay after Transfer Prescaler value is 5.
11 Delay after Transfer Prescaler value is 7.
Baud Rate Prescaler
Selects the prescaler value for the baud rate. This field is used only in master mode. The baud rate is the
frequency of the SCK. The system clock is divided by the prescaler value before the baud rate selection
takes place. See the BR field description for details on how to compute the baud rate.
00 Baud Rate Prescaler value is 2.
01 Baud Rate Prescaler value is 3.
10 Baud Rate Prescaler value is 5.
11 Baud Rate Prescaler value is 7.
PCS to SCK Delay Scaler
Selects the scaler value for the PCS to SCK delay. This field is used only in master mode. The PCS to
SCK Delay is the delay between the assertion of PCS and the first edge of the SCK. The delay is a
multiple of the system clock period, and it is computed according to the following equation:
t_CSC = (1/f_SYS) x PCSSCK x CSSCK
The following table lists the delay scaler values.
Table 49-33. Delay Scaler Encoding
Field Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
Delay Scaler Value
2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
16384
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1405