K60P100M100SF2RM Datasheet, PDF (547/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
5
PLLSTEN
4–0
PRDIV
Chapter 24 Multipurpose Clock Generator (MCG)
MCG_C5 field descriptions (continued)
0 MCGPLLCLK is inactive.
1 _{MCGPLLCLK is active.}
PLL Stop Enable
Description
Enables the PLL Clock during Normal Stop (In Low Power Stop mode, the PLL clock gets disabled
even if PLLSTEN =1). All other power modes, PLLSTEN bit has no affect and does not enable the PLL
Clock to run if it is written to 1.
0 MCGPLLCLK is disabled in any of the Stop modes.
1 _{MCGPLLCLK is enabled if system is in Normal Stop mode.}
PLL External Reference Divider
Selects the amount to divide down the external reference clock for the PLL. The resulting frequency
must be in the range of 2 MHz to 4 MHz. After the PLL is enabled (by setting either PLLCLKEN or
PLLS), the PRDIV value must not be changed when LOCK is zero.
Table 24-7. PLL External Reference Divide Factor
PRDIV Divide
Factor
00000 1
00001 2
00010 3
00011 4
00100 5
00101 6
00110 7
00111 8
PRDIV Divide
Factor
01000 9
01001 10
01010 11
01011 12
01100 13
01101 14
01110 15
01111 16
PRDIV Divide
Factor
10000 17
10001 18
10010 19
10011 20
10100 21
10101 22
10110 23
10111 24
PRDIV Divide
Factor
11000 25
11001 Reserv
ed
11010 Reserv
ed
11011 Reserv
ed
11100 Reserv
ed
11101 Reserv
ed
11110 Reserv
ed
11111 Reserv
ed
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
547