K60P100M100SF2RM Datasheet, PDF (1066/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Description
PIT memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access
Reset value
4003_7130 Timer Load Value Register (PIT_LDVAL3)
32
R/W 0000_0000h
4003_7134 Current Timer Value Register (PIT_CVAL3)
32
R/W 0000_0000h
4003_7138 Timer Control Register (PIT_TCTRL3)
32
R/W 0000_0000h
4003_713C Timer Flag Register (PIT_TFLG3)
32
R/W 0000_0000h
Section/
page
40.3.2/
1067
40.3.3/
1067
40.3.4/
1068
40.3.5/
1068
40.3.1 PIT Module Control Register (PIT_MCR)
This register controls whether the timer clocks should be enabled and whether the timers
should run in debug mode.
Address: PIT_MCR is 4003_7000h base + 0h offset = 4003_7000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
PIT_MCR field descriptions
Field
31–2
Reserved
1
MDIS
Description
This read-only field is reserved and always has the value zero.
Module Disable
This is used to disable the module clock. This bit must be enabled before any other setup is done.
0 Clock for PIT Timers is enabled.
1 Clock for PIT Timers is disabled.
0
Freeze
FRZ
Allows the timers to be stopped when the device enters debug mode.
0 Timers continue to run in debug mode.
1 Timers are stopped in debug mode.
1066
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.