K60P100M100SF2RM Datasheet, PDF (493/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 21 Direct Memory Access Controller (eDMA)
PEAKreq = 150 MHz / [ 4 + (1 + 1) + (1 + 3) + 3 ] cycles = 11.5 Mreq/sec
For an internal peripheral bus to SRAM transfer,
PEAKreq = 150 MHz / [ 4 + (1 + 2) + (1 + 1) + 3 ] cycles = 12.5 Mreq/sec
Assuming an even distribution of the two transfer types, the average peak request rate
would be:
PEAKreq = (11.5 Mreq/sec + 12.5 Mreq/sec) / 2 = 12.0 Mreq/sec
The minimum number of cycles to perform a single read/write, zero wait states on the
system bus, from a cold start where no channel is executing and eDMA is idle are:
• 11 cycles for a software, that is, a TCDn_CSR[START] bit, request
• 12 cycles for a hardware, that is, an eDMA peripheral request signal, request
Two cycles account for the arbitration pipeline and one extra cycle on the hardware
request resulting from the internal registering of the eDMA peripheral request signals.
For the peak request rate calculations above, the arbitration and request registering is
absorbed in or overlaps the previous executing channel.
Note
When channel linking or scatter/gather is enabled, a two cycle
delay is imposed on the next channel selection and startup. This
allows the link channel or the scatter/gather channel to be
eligible and considered in the arbitration pool for next channel
selection.
21.5 Initialization/application information
The following sections discuss initialization of the eDMA and programming
considerations.
21.5.1 eDMA initialization
A typical initialization of the eDMA has the following sequence:
1. Write the CR register if a configuration other than the default is desired.
2. Write the channel priority levels into the DCHPRIn registers if a configuration other
than the default is desired.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
493