K60P100M100SF2RM Datasheet, PDF (592/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register descriptions
Table 27-3. Program visible cache registers
Cache
storage
Tag
Based at
offset
Contents of 32-bit read
100h
13'h0, tag[18:6], 5'h0, valid
Data
200h
Upper or lower word of data
Nomenclature
Nomenclature example
In TAGVDWxSy, x denotes the way TAGVDW2S0 is the 13-bit
and y denotes the set.
tag and 1-bit valid for cache
entry way 2, set 0.
In DATAWxSyU and DATAWxSyL,
x denotes the way, y denotes the
set, and U and L represent upper
and lower word, respectively.
DATAW1S0U represents bits
[63:32] of data entry way 1,
set 0, and DATAW1S0L
represents bits [31:0] of data
entry way 1, set 0.
Absolute
address
(hex)
FMC memory map
Register name
Width
(in bits)
Access
Reset value
4001_F000 Flash Access Protection Register (FMC_PFAPR)
32
R/W 00F8_003Fh
4001_F004 Flash Bank 0 Control Register (FMC_PFB0CR)
32
R/W 3002_001Fh
4001_F008 Flash Bank 1 Control Register (FMC_PFB1CR)
32
R/W 3002_001Fh
4001_F100 Cache Tag Storage (FMC_TAGVDW0S0)
32
R/W 0000_0000h
4001_F104 Cache Tag Storage (FMC_TAGVDW0S1)
32
R/W 0000_0000h
4001_F108 Cache Tag Storage (FMC_TAGVDW0S2)
32
R/W 0000_0000h
4001_F10C Cache Tag Storage (FMC_TAGVDW0S3)
32
R/W 0000_0000h
4001_F110 Cache Tag Storage (FMC_TAGVDW0S4)
32
R/W 0000_0000h
4001_F114 Cache Tag Storage (FMC_TAGVDW0S5)
32
R/W 0000_0000h
4001_F118 Cache Tag Storage (FMC_TAGVDW0S6)
32
R/W 0000_0000h
4001_F11C Cache Tag Storage (FMC_TAGVDW0S7)
32
R/W 0000_0000h
4001_F120 Cache Tag Storage (FMC_TAGVDW1S0)
32
R/W 0000_0000h
4001_F124 Cache Tag Storage (FMC_TAGVDW1S1)
32
R/W 0000_0000h
4001_F128 Cache Tag Storage (FMC_TAGVDW1S2)
32
R/W 0000_0000h
4001_F12C Cache Tag Storage (FMC_TAGVDW1S3)
32
Table continues on the next page...
R/W 0000_0000h
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
592
Freescale Semiconductor, Inc.