K60P100M100SF2RM Datasheet, PDF (1123/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 43 Real Time Clock (RTC)
The time seconds register and time prescaler register can only be written when the
SR[TCE] bit is clear. Always write to the prescaler register before writing to the seconds
register, since the seconds register increments on the falling edge of bit 14 of the
prescaler register.
The time prescaler register increments provided the SR[TCE] bit is set, the SR[TIF] is
clear, the SR[TOF] is clear and the 32.768 kHz clock source is present. After enabling the
oscillator, wait the oscillator startup time before setting the SR[TCE] bit to allow time for
the oscillator clock output to stabilize.
If the time seconds register overflows then the SR[TOF] will set and the time prescaler
register will stop incrementing. Clear the SR[TOF] by initializing the time seconds
register. The time seconds register and time prescaler register read as zero whenever the
SR[TOF] is set.
The SR[TIF] is set on VBAT POR and software reset and is cleared by initializing the
time seconds register. The time seconds register and time prescaler register read as zero
whenever the SR[TIF] is set.
43.3.3 Compensation
The compensation logic provides an accurate and wide compensation range and can
correct errors as high as 3906 ppm and as low as 0.12 ppm. Note that the compensation
factor must be calculated externally to the RTC and supplied by software to the
compensation register. The RTC itself does not calculate the amount of compensation
that is required, although the 1 Hz clock is output to an external pin in support of external
calibration logic.
Crystal compensation can be supported by using firmware and crystal characteristics to
determine the compensation amount. Temperature compensation can be supported by
firmware that periodically measures the external temperature (via ADC) and updates the
compensation register based on a look-up table that specifies the change in crystal
frequency over temperature.
The compensation logic alters the number of 32.768 kHz clock cycles it takes for the
prescaler register to overflow and increment the time seconds counter. The time
compensation value is used to adjust the number of clock cycles between -127 and +128.
Cycles are added or subtracted from the prescaler register when the prescaler register
equals 0x3FFF and then increments. The compensation interval is used to adjust the
frequency at which the time compensation value is used (from once a second to once
every 256 seconds).
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1123