K60P100M100SF2RM Datasheet, PDF (1503/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
6
MAEN2
5
M10
4–0
BRFA
Chapter 51 Universal Asynchronous Receiver/Transmitter (UART)
UARTx_C4 field descriptions (continued)
Description
0 All data received is transferred to the data buffer if MAEN2 is cleared.
1 All data received with the most significant bit cleared, is discarded. All data received with the most
significant bit set, is compared with contents of MA1 register. If no match occurs, the data is
discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when
C7816[ISO7816E] is set/enabled.
Match Address Mode Enable 2
Refer to Match address operation for more information.
0 All data received is transferred to the data buffer if MAEN1 is cleared.
1 All data received with the most significant bit cleared, is discarded. All data received with the most
significant bit set, is compared with contents of MA2 register. If no match occurs, the data is
discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when
C7816[ISO7816E] is set/enabled.
10-bit Mode select
The M10 bit causes a tenth, non-memory mapped bit to be part of the serial transmission. This tenth bit is
generated and interpreted as a parity bit. The M10 bit does not affect the LIN send or detect break
behavior. If M10 is set then both C1[M] and C1[PE] bits must also be set. This bit must be cleared when
C7816[ISO7816E] is set/enabled. Refer to Data format (non ISO-7816) for more information.
0 The parity bit is the ninth bit in the serial transmission.
1 The parity bit is the tenth bit in the serial transmission.
Baud Rate Fine Adjust
This bit field is used to add more timing resolution to the average baud frequency, in increments of 1/32.
Refer to Baud rate generation for more information.
51.3.12 UART Control Register 5 (UARTx_C5)
Addresses: UART0_C5 is 4006_A000h base + Bh offset = 4006_A00Bh
UART1_C5 is 4006_B000h base + Bh offset = 4006_B00Bh
UART2_C5 is 4006_C000h base + Bh offset = 4006_C00Bh
UART3_C5 is 4006_D000h base + Bh offset = 4006_D00Bh
UART4_C5 is 400E_A000h base + Bh offset = 400E_A00Bh
Bit
7
6
5
4
3
2
1
Read
0
0
TDMAS
RDMAS
Write
Reset
0
0
0
0
0
0
0
UARTx_C5 field descriptions
Field
7
TDMAS
Transmitter DMA Select
Description
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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0
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