K60P100M100SF2RM Datasheet, PDF (823/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 34 Analog-to-Digital Converter (ADC)
34.3.18 ADC PGA register (ADCx_PGA)
Addresses: ADC0_PGA is 4003_B000h base + 50h offset = 4003_B050h
ADC1_PGA is 400B_B000h base + 50h offset = 400B_B050h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
W
0
0
PGAG
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADCx_PGA field descriptions
Field
31–24
Reserved
23
PGAEN
22
Reserved
21
Reserved
20
PGALPb
19–16
PGAG
Description
This read-only field is reserved and always has the value zero.
PGA enable
0 PGA disabled.
1 PGA enabled.
This read-only field is reserved and always has the value zero.
This field is reserved.
PGA low-power mode control
0 PGA runs in low power mode.
1 PGA runs in normal power mode.
PGA gain setting
PGA gain = 2^(PGAG)
0000
0001
0010
0011
0100
0101
0110
0111
1
2
4
8
16
32
64
Reserved
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
823