K60P100M100SF2RM Datasheet, PDF (107/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 3 Chip Configuration
The backdoor port makes the SRAM accessible to the non-core bus masters (such as
DMA).
The following figure illustrates the SRAM accesses within the device.
Cortex-M4 core
Code bus
System bus
Frontdoor
MPU
SRAM_L
SRAM controller
Backdoor
MPU
Crossbar switch
non-core master
non-core master
non-core master
SRAM_U
Figure 3-26. SRAM access diagram
The following simultaneous accesses can be made to different logical halves of the
SRAM:
• Core code and core system
• Core code and non-core master
• Core system and non-core master
NOTE
Two non-core masters cannot access SRAM simultaneously.
The required arbitration and serialization is provided by the
crossbar switch. The SRAM_{L,U} arbitration is controlled by
the SRAM controller based on the configuration bits in the
MCM module.
NOTE
Burst-access cannot occur across the 0x2000_0000 boundary
that separates the two SRAM arrays. The two arrays should be
treated as separate memory ranges for burst accesses.
3.5.3.5 SRAM arbitration and priority control
The MCM's SRAMAP register controls the arbitration and priority schemes for the two
SRAM arrays.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
107