K60P100M100SF2RM Datasheet, PDF (881/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 35 Comparator (CMP)
Table 35-30. Comparator Sample/Filter Maximum Latencies (continued)
Mode #
7
CR1[
EN]
1
CR1[
WE]
1
CR1[
SE]
0
CR0[FILTER
_CNT]
> 0x01
FPR[FILT_P
ER]
0x01 - 0xFF
Operation
Windowed / Filtered mode
Maximum Latency¹
T_PD + (CR0[FILTER_CNT] x
FPR[FILT_PER] x T_per) +
2T_per
1. T_PD represents the intrinsic delay of the analog component plus the polarity select logic. T_SAMPLE is the clock period of the
external sample clock. T_per is the period of the bus clock.
35.9 CMP Interrupts
The CMP module is capable of generating an interrupt on either the rising or falling edge
of the comparator output (or both). The interrupt request is asserted when both SCR[IER]
bit and SCR[CFR] are set. It is also asserted when both SCR[IEF] bit and SCR[CFF] are
set. The interrupt is de-asserted by clearing either SCR[IER] or SCR[CFR] for a rising
edge interrupt, or SCR[IEF] and SCR[CFF] for a falling edge interrupt.
35.10 CMP DMA Support
Normally, the CMP generates a CPU interrupt if there is a change on the COUT. When
DMA support (set SCR[DMAEN]) enables and the interrupt enables (set SCR[IER] or
SCR[IEF] or both), the corresponding change on COUT forces a DMA transfer request
rather than a CPU interrupt instead. When the DMA has completed the transfer, it sends a
dma_done signal that de-asserts the dma_request and clears the flag to allow a
subsequent change on comparator output to occur and force another DMA request.
35.11 Digital to Analog Converter Block Diagram
The following figure shows the block diagram of the DAC module. It contains a 64-tap
resistor ladder network and a 64-to-1 multiplexer, which selects an output voltage from
one of 64 distinct levels that outputs from DACO. It is controlled through DAC Control
register (DACCR). Its supply reference source can be selected from two sources V_in1 and
V_in2. The module can be powered down (disabled) when it is not used. When in disable
mode, DACO is connected to the analog ground.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
881