K60P100M100SF2RM Datasheet, PDF (903/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

37.3.2.1 SC[MODE_LV]=00
Chapter 37 Voltage Reference (VREFV1)
The internal bandgap is enabled to generate an accurate 1.2 V output that can be trimmed
with the TRM register's TRIM[5:0] bitfield. The bandgap requires some time for startup
and stabilization. SC[VREFST] can be monitored to determine if the stabilization and
startup is complete.
The output buffer is disabled in this mode, and there is no buffered voltage output. The
Voltage Reference is in standby mode. If this mode is first selected and the tight
regulation buffer mode is subsequently enabled, there will be a delay before the buffer
output is settled at the final value. This is the buffer start up delay (Tstup) and the value is
specified in the appropriate device data sheet.
37.3.2.2 SC[MODE_LV] = 01
Reserved
37.3.2.3 SC[MODE_LV] = 10
The tight regulation buffer is enabled to generate a buffered 1.2 V voltage to
VREF_OUT. If this mode is entered from the standby mode (SC[MODE_LV] = 00,
SC[VREFEN] = 1) there will be a delay before the buffer output is settled at the final
value. This is the buffer start up delay (Tstup) and the value is specified in the
appropriate device data sheet. If this mode is entered when the VREF module is enabled
then you must wait the longer of Tstup or until SC[VREFST] = 1.
37.3.2.4 SC[MODE_LV] = 11
Reserved
37.4 Initialization/Application Information
The Voltage Reference requires some time for startup and stabilization. After
SC[VREFEN] = 1, SC[VREFST] can be monitored to determine if the stabilization and
startup of the VREF bandgap is complete.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
903