K60P100M100SF2RM Datasheet, PDF (520/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Overview
Updates in the write–once registers take effect only after the WCT window closes with
the following exceptions for which changes take effect immediately:
• the stop, wait, and debug mode enable bits
• the standby mode enable bit
• the IRQ_RST_EN bit
The operations of refreshing the watchdog goes undetected during the WCT.
23.3.3 Refreshing the Watchdog
A robust refreshing mechanism has been chosen for the watchdog. A valid refresh is a
write of 0xA602 followed by 0xB480 within 20 bus clock cycles to watchdog refresh
register. If these two values are written more than 20 bus cycles apart or if something
other than these two values is written to the register, a watchdog reset (or interrupt-then-
reset if enabled) is issued to the system. A valid refresh makes the watchdog timer restart
on the next bus clock. Also, an attempted unlock operation, in between the two writes of
the refresh sequence goes undetected. See Watchdog Operation with 8-bit access for
guidelines related to 8-bit accesses to the refresh register.
23.3.4 Windowed Mode of Operation
In this mode of operation a restriction is placed on the point in time within the time-out
period at which the watchdog can be refreshed. The refresh is considered valid only when
the watchdog timer increments beyond a certain count as specified by the watchdog
window register. This is known as refreshing the watchdog within a window of the total
time-out period. If a refresh is attempted before the timer reaches the window value, the
watchdog generates a reset (or interrupt-then-reset if enabled). Of course, if there is no
refresh at all, the watchdog times out and generates a reset or interrupt-then-reset if
enabled.
23.3.5 Watchdog Disabled Mode of Operation
When the watchdog is disabled through the WDOG_EN bit in the watchdog status and
control register, the watchdog timer is reset to zero and is disabled from counting until
you enable it or it is again enabled by the system reset. In this mode the watchdog timer
cannot be refreshed (there is no requirement to do so while the timer is disabled).
However, the watchdog still generates a reset (or interrupt-then-reset if enabled) on a
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
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Freescale Semiconductor, Inc.