K60P100M100SF2RM Datasheet, PDF (264/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
PORTx_ISFR field descriptions
Field
31–0
ISF
Interrupt Status Flag
Description
Each bit in the field indicates the detection of the configured interrupt of the same number as the bit.
0 Configured interrupt has not been detected.
1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the
corresponding flag will be cleared automatically at the completion of the requested DMA transfer,
otherwise the flag remains set until a logic one is written to the flag. If configured for a level sensitive
interrupt and the pin remains asserted then the flag will set again immediately after it is cleared.
11.4.5 Digital Filter Enable Register (PORTx_DFER)
Addresses: PORTA_DFER is 4004_9000h base + C0h offset = 4004_90C0h
PORTB_DFER is 4004_A000h base + C0h offset = 4004_A0C0h
PORTC_DFER is 4004_B000h base + C0h offset = 4004_B0C0h
PORTD_DFER is 4004_C000h base + C0h offset = 4004_C0C0h
PORTE_DFER is 4004_D000h base + C0h offset = 4004_D0C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DFE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PORTx_DFER field descriptions
Field
31–0
DFE
Digital Filter Enable
Description
The digital filter configuration is valid in all digital pin muxing modes. The output of each digital filter is
reset to zero at system reset and whenever the digital filter is disabled.
0 Digital Filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each
bit in the field enables the digital filter of the same number as the bit.
1 Digital Filter is enabled on the corresponding pin, provided pin is configured as a digital input.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
264
Freescale Semiconductor, Inc.