K60P100M100SF2RM Datasheet, PDF (1196/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
• Stops sending data for the amount of time specified by the pause quanta in 512 bit
time increments
• Sets ENETn_TCR[RFC_PAUSE]
Frame transfer resumes when the time specified by the quanta expireds and if no new
quanta value is received or if a new pause frame with a quanta value set to 0x0000 is
received. The MAC also resets RFC_PAUSE to zero.
If ENETn_RCR[FCE] cleared, the MAC ignores received pause frames.
Optionally and independent of ENETn_RCR[FCE], pause frames are forwarded to the
client interface if PAUFWD is set.
44.4.6.2 Local Device/FIFO Congestion
The MAC transmit engine generates pause frames when the local receive FIFO is not
able to receive more than a pre-defined number of words (FIFO programmable threshold)
or when pause frame generation is requested by the local host processor.
• To generate a pause frame, the host processor sets ENETn_TCR[TFC_PAUSE]. A
single pause frame is generated when the current frame transfer is completed and
TFC_PAUSE is automatically cleared. Optionally, an interrupt is generated.
• A XOFF pause frame is generated when the receive FIFO asserts its section empty
flag (internal). A XOFF pause frame is generated automatically, when the current
frame transfer completes.
• A XON pause frame is generated when the receive FIFO deasserts its section empty
flag (internal). A XON pause frame is generated automatically, when the current
frame transfer completes.
When a XOFF pause frame is generated, the pause quanta (payload byte P1 and P2) is
filled with the value programmed in ENETn_OPD[PAUSE_DUR].
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.