K60P100M100SF2RM Datasheet, PDF (732/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BE/BWEn
FB_TA
FB_TSIZ[1:0]
Address
Address
Add+1
Add+2
Data
Data
Data
Add+3
Data
AA=1
AA=0
AA=1
AA=0
TSIZ = 11
Figure 29-45. 32-bit-Read Burst from 8-Bit Port 2-1-1-1 (No Wait States)
The following figure shows a 32-bit write to an 8-bit device with burst enabled. The
transfer results in a 4-beat burst and the data is driven on FB_AD[31:24]. The transfer
size is driven at 32-bit (00) throughout the bus cycle.
Note
The first beat of any write burst cycle has at least one wait state.
If the bus cycle is programmed for zero wait states
(CSCRn[WS] = 0), one wait state is added. Otherwise, the
programmed number of wait states are used.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
732
Freescale Semiconductor, Inc.