K60P100M100SF2RM Datasheet, PDF (1716/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map/register definition
I2Sx_RMSK field descriptions
Field
31–0
RMSK
Receive Mask.
Description
These bits indicate which slot has been masked in the current frame. The Core can write to this register to
control the time slots in which the I²S receives data. Each bit has info corresponding to the respective
time slot in the frame. RMSK register value must be set before enabling Receiver.Receive mask bits
should not be used in I2S Slave mode of operation.
0 Valid Time Slot.
1 Time Slot masked (no data received in this time slot).
53.3.19 I²S AC97 Channel Status Register (I2Sx_ACCST)
Addresses: I2S0_ACCST is 4002_F000h base + 50h offset = 4002_F050h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
ACCST
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_ACCST field descriptions
Field
31–10
Reserved
9–0
ACCST
Description
This read-only field is reserved and always has the value zero.
AC97 Channel Status.
These bits indicate which data slot has been enabled in AC97 variable mode operation. This register is
updated in case the core enables/disables a channel through a write to ACCEN/ACCDIS register or the
external codec enables a channel by sending a `1' in the corresponding SLOTREQ bit. Bit [0] corresponds
to the first data slot in an AC97 frame (Slot #3) and Bit [9] corresponds to the tenth data slot (slot #12).
The contents of this register only have relevance while the I²S is operating in AC97 variable mode. Writes
to this register result in an error response on the IP interface.
0 Data channel disabled.
1 Data channel enabled.
53.3.20 I²S AC97 Channel Enable Register (I2Sx_ACCEN)
Addresses: I2S0_ACCEN is 4002_F000h base + 54h offset = 4002_F054h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
0
W
ACCEN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1716
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.