K60P100M100SF2RM Datasheet, PDF (696/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Signal Descriptions
29.2.2 Chip Selects (FB_CS[5 :0])
The chip-select signal indicates which device is selected. A particular chip-select asserts
when the transfer address is within the device's address space, as defined in the base- and
mask-address registers. The actual number of chip selects available depends upon the pin
configuration.
29.2.3 Byte Enables (FB_BE_31_24, FB_BE_23_16, FB_BE_15_8,
FB_BE_7_0)
When driven low, the byte enable outputs indicate data is to be latched or driven onto a
specific byte lane of the data bus. A configuration option is provided to assert these
signals on reads and writes or writes only.
For external SRAM or flash devices, the FB_BEn outputs must be connected to
individual byte strobe signals.
29.2.4 Output Enable (FB_OE)
The output enable signal (FB_OE) is sent to the interfacing memory and/or peripheral to
enable a read transfer. FB_OE is only asserted during read accesses when a chip select
matches the current address decode.
29.2.5 Read/Write (FB_R/W)
The processor drives the FB_R/W signal to indicate the current bus operation direction. It
is driven high during read bus cycles and low during write bus cycles.
29.2.6 Transfer Start/Address Latch Enable (FB_TS/FB_ALE)
The assertion of FB_TS indicates that the device has begun a bus transaction and the
address and attributes are valid.
In multiplexed mode, an inverted FB_TS (FB_ALE) is available as an address latch
enable, which indicates when the address is being driven on the FB_AD bus.
FB_TS/FB_ALE is asserted for one bus clock cycle.
This device can extend this signal until the first positive clock edge after FB_CSn asserts.
See CSCRn[EXTS] and Extended Transfer Start/Address Latch Enable.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
696
Freescale Semiconductor, Inc.