K60P100M100SF2RM Datasheet, PDF (1011/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

system clock
write 1 to SWSYNC bit
Chapter 39 FlexTimer (FTM)
SWSYNC bit
software trigger event
PWM synchronization
selected loading point
Figure 39-206. Software Trigger Event
39.4.11.3 Boundary Cycle and Loading Points
The boundary cycle definition is important for the loading points for the registers MOD,
CNTIN and C(n)V.
In up counting mode (Up Counting) the boundary cycle is defined as when the counter
wraps to its initial value (CNTIN). If in up-down counting mode (Up-Down Counting)
then the boundary cycle is defined as when the counter turns from down to up counting
and when from up to down counting.
The following figure shows the boundary cycles and the loading points. In the up
counting mode, the loading points are enabled if one of CNTMIN or CTMAX bits are 1.
In the up-down counting mode, the loading points are selected by CNTMIN and
CNTMAX bits, as indicated in the figure. These loading points are safe places for register
updates thus allowing a smooth transitions in PWM waveform generation.
For both counting modes if neither CNTMIN nor CNTMAX are 1 then the boundary
cycles are not used as loading points for registers updates. See the register
synchronization descriptions in the following sections for details.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1011