K60P100M100SF2RM Datasheet, PDF (306/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Introduction
13.1.2 Modes of Operation
The ARM CPU has three primary modes of operation: run, sleep, and deep sleep. The
WFI instruction is used to invoke sleep and deep sleep modes. For Freescale
microcontrollers, run, wait and stop are the common terminology used for the primary
operating modes. The following table shows the translation between the ARM CPU and
the MCU power modes.
ARM CPU mode
Sleep
Deep sleep
MCU mode
Wait
Stop
Accordingly, the ARM CPU documentation refers to sleep and deep sleep, while the
Freescale MCU documentation normally uses wait and stop.
This device augments stop, wait, and run in a number of ways. The power management
controller (PMC) contains a run and a stop mode regulator. Run regulation is used in
normal run, wait and stop modes. Stop mode regulation is used during all very low power
and low leakage modes. During stop mode regulation the bus frequencies are limited for
the very low power modes.
The PMC provides the user with multiple power options. The low power operating modes
can drastically reduce run time power when maximum bus frequency is not required to
handle the application needs. From normal run mode, the run mode (RUNM) bit field can
be modified to change the the MCU into the very lower power run (VLPR) mode when
limited frequency is required during the application. For the low power run mode, a
corresponding wait and stop mode can be entered.
Depending on the needs of the user application, a variety of stop modes are available that
allow the state retention, partial power down or full power down of certain logic and/or
memory. I/O states are held in all modes of operation. Several registers are used to
configure the various modes of operation for the device.
The following table describes the power modes available for the device.
Table 13-1. Power modes
Mode
Run
Wait
Stop
Description
MCU can be run at full speed and the internal supply is fully regulated (run regulation mode). This
mode is also referred to as normal run mode.
In ARM architectures, the Core Clock to the ARM Cortex-M4 core is shut off. The System Clock
continues to operate; Bus Clocks if enabled continue to operate; run regulation is maintained.
In ARM architectures, Core Clock and System Clock to the ARM Cortex-M4 core shut off
immediately.System Clock to other masters and Bus Clocks are stopped after all stop acknowledge
signals from supporting peripherals are valid.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
306
Freescale Semiconductor, Inc.