K60P100M100SF2RM Datasheet, PDF (1371/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 48 CAN (FlexCAN)
FlexCAN. CPU must maintain data coherency in the FIFO
region when RFEN is asserted.
48.4.6.3 Message Buffer Lock Mechanism
Besides MB inactivation, FlexCAN has another data coherence mechanism for the
receive process. When the CPU reads the Control and Status word of an Rx MB with
codes FULL or OVERRUN, FlexCAN assumes that the CPU wants to read the whole
MB in an atomic operation, and thus it sets an internal lock flag for that MB. The lock is
released when the CPU reads the Free Running Timer (global unlock operation), or when
it reads the Control and Status word of another MB regardless of its code, or when the
CPU writes into C/S word from locked MB. The MB locking is done to prevent a new
frame to be written into the MB while the CPU is reading it.
NOTE
The locking mechanism only applies to Rx MBs that are not
part of FIFO and have a code different than INACTIVE
(0b0000) or EMPTY¹ (0b0100). Also, Tx MBs can not be
locked.
Suppose, for example, that the FIFO is disabled and the second and the fifth MBs of the
array are programmed with the same ID, and FlexCAN has already received and stored
messages into these two MBs. Suppose now that the CPU decides to read MB number 5
and at the same time another message with the same ID is arriving. When the CPU reads
the Control and Status word of MB number 5, this MB is locked. The new message
arrives and the matching algorithm finds out that there are no "free-to-receive" MBs, so it
decides to override MB number 5. However, this MB is locked, so the new message can
not be written there. It will remain in the SMB waiting for the MB to be unlocked, and
only then will be written to the MB. If the MB is not unlocked in time and yet another
new message with the same ID arrives, then the new message overwrites the one on the
SMB and there will be no indication of lost messages either in the CODE field of the MB
or in the Error and Status Register.
While the message is being moved-in from the SMB to the MB, the BUSY bit on the
CODE field is asserted. If the CPU reads the Control and Status word and finds out that
the BUSY bit is set, it should defer accessing the MB until the BUSY bit is negated.
Note
If the BUSY bit is asserted or if the MB is empty, then reading
the Control and Status word does not lock the MB.
1. In previous FlexCAN versions, reading the C/S word locked the MB even if it was
EMPTY. This behavior is maintained when the IRMQ bit is negated.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1371