K60P100M100SF2RM Datasheet, PDF (563/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 24 Multipurpose Clock Generator (MCG)
24.5.2 Using a 32.768 kHz Reference
In FEE and FBE modes, if using a 32.768 kHz external reference, at the default FLL
multiplication factor of 640, the DCO output (MCGFLLCLK) frequency is 20.97 MHz at
low-range. If C4[DRST_DRS] bits are set to 2'b01, the multiplication factor is doubled to
1280, and the resulting DCO output frequency is 41.94 Mhz at mid-low-range. If
C4[DRST_DRS] bits are set to 2'b10, the multiplication factor is set to 1920, and the
resulting DCO output frequency is 62.91 MHz at mid high-range. If C4[DRST_DRS] bits
are set to 2'b11, the multiplication factor is set to 2560, and the resulting DCO output
frequency is 83.89 MHz at high-range.
In FBI and FEI modes, setting C4[DMX32] bit is not recommended. If the internal
reference is trimmed to a frequency above 32.768 kHz, the greater FLL multiplication
factor could potentially push the microcontroller system clock out of specification and
damage the part.
The RTC 32 kHz oscillator may be used as the FLL reference clock. Refer to the SIM
chapter on how this can be selected. The MCG must be in an internal clocking mode
(FEI, FBI or BLPI) when the external clock selection mux is switched. The C2[RANGE]
bits must be set to 2'b00 and the C1[FRDIV] bits must be set to 3'b000 to ensure this
clock is divided by 1 to keep it within the allowed FLL reference clock range.
24.5.3 MCG Mode Switching
When switching between operational modes of the MCG, certain configuration bits must
be changed in order to properly move from one mode to another. Each time any of these
bits are changed (C6[PLLS], C1[IREFS], C1[CLKS], C2[IRCS], or C2[EREFS]), the
corresponding bits in the MCG status register (PLLST, IREFST, CLKST, IRCST, or
OSCINIT) must be checked before moving on in the application software.
Additionally, care must be taken to ensure that the reference clock divider (C1[FRDIV]
and C5[PRDIV]) is set properly for the mode being switched to. For instance, in PEE
mode, if using a 4 MHz crystal, C5[PRDIV] must be set to 5'b000 (divide-by-1) or
5'b001 (divide -by-2) in order to divide the external reference down to the required
frequency between 2 and 4 MHz.
In FBE, FEE, FBI, and FEI modes, at any time, the application can switch the FLL
multiplication factor between 640, 1280, 1920, and 2560 with C4[DRST_DRS] bits.
Writes to C4[DRST_DRS] bits will be ignored if C2[LP]=1.
The table below shows MCGOUTCLK frequency calculations using C1[FRDIV],
C5[PRDIV], and C6[VDIV] settings for each clock mode.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
563