K60P100M100SF2RM Datasheet, PDF (1200/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
The MAC usually removes padding on receive when a frame with length information is
received. As IP frames have a type value instead of length, the MAC does not remove
padding for short IP frames, as it is not aware of the frame contents.
The IP accelerator function can be configured to remove the Ethernet padding bytes that
might follow the IP datagram.
On transmit, the MAC automatically adds padding as necessary to fill any frame to a 64-
byte length.
44.4.8.3 32-bit Ethernet Payload Alignment
The data FIFOs allow inserting two additional arbitrary bytes in front of a frame. This
extends the 14-byte Ethernet header to a 16-byte header, which leads to alignment of the
Ethernet payload, following the Ethernet header, on a 32-bit boundary.
This function can be enabled for transmit and receive independently with the
corresponding SHIFT16 bits in the ENETn_TACC and ENETn_RACC registers.
When enabled, the valid frame data is arranged as shown in this table.
Table 44-78. 64-Bit Interface Data Structure with SHIFT16 Enabled
63 56
Byte 5
Byte 13
55 48
Byte 4
Byte 12
47 40
Byte 3
Byte 11
39 32
Byte 2
Byte 10
...
31 24
Byte 1
Byte 9
23 16
Byte 0
Byte 8
15 8
Any value
Byte 7
70
Any value
Byte 6
44.4.8.3.1 Receive Processing
When ENETn_RACC[SHIFT16] is set, each frame is received with two additional bytes
in front of the frame.
The user application must ignore these first two bytes and find the first byte of the frame
in bits 23–16 of the first word from the RX FIFO.
Note
SHIFT16 must be set during initialization and kept set during
the complete operation, as it influences the FIFO write
behavior.
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.