K60P100M100SF2RM Datasheet, PDF (364/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map / Register Definition
17.2 Memory Map / Register Definition
Each slave port of the crossbar switch contains configuration registers. Read- and write-
transfers require two bus clock cycles. The registers can be read from and written to only
in supervisor mode. Additionally, these registers can be read from or written to only by
32-bit accesses.
A bus error response is returned if an unimplemented location is accessed within the
crossbar switch.
The slave registers also feature a bit that, when set, prevents the registers from being
written. The registers remain readable, but future write attempts have no effect on the
registers and are terminated with a bus error response to the master initiating the write.
The core, for example, takes a bus error interrupt.
NOTE
This section shows the registers for all eight master and slave
ports. If a master or slave is not used on this particular device,
then unexpected results occur when writing to its registers. See
the chip configuration details for the exact master/slave
assignments for your device.
AXBS memory map
Absolute
address
(hex)
Register name
4000_4000 Priority Registers Slave (AXBS_PRS0)
4000_4010 Control Register (AXBS_CRS0)
4000_4100 Priority Registers Slave (AXBS_PRS1)
4000_4110 Control Register (AXBS_CRS1)
4000_4200 Priority Registers Slave (AXBS_PRS2)
4000_4210 Control Register (AXBS_CRS2)
4000_4300 Priority Registers Slave (AXBS_PRS3)
4000_4310 Control Register (AXBS_CRS3)
4000_4400 Priority Registers Slave (AXBS_PRS4)
4000_4410 Control Register (AXBS_CRS4)
4000_4500 Priority Registers Slave (AXBS_PRS5)
4000_4510 Control Register (AXBS_CRS5)
Width
(in bits)
Access
Reset value
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
364
Freescale Semiconductor, Inc.