K60P100M100SF2RM Datasheet, PDF (103/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 3 Chip Configuration
3.5.1.7 Erase All Flash Contents
In addition to software, the entire flash memory may be erased external to the flash
memory in two ways:
1. Via the EzPort by issuing a bulk erase (BE) command. See the EzPort chapter for
more details.
2. Via the SWJ-DP debug port by setting DAP_CONTROL[0]. DAP_STATUS[0] is set
to indicate the mass erase command has been accepted. DAP_STATUS[0] is cleared
when the mass erase completes.
3.5.1.8 FTFL_FOPT Register
The flash memory's FTFL_FOPT register allows the user to customize the operation of
the MCU at boot time. See FOPT boot options for details of its definition.
3.5.2 Flash Memory Controller Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral bus
controller 0
Register
access
Transfers
Flash memory
controller
Transfers
Figure 3-23. Flash memory controller configuration
Topic
Full description
System memory map
Clocking
Transfers
Table 3-36. Reference links to related information
Related module
Flash memory
controller
Flash memory
Reference
Flash memory controller
System memory map
Clock Distribution
Flash memory
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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