K60P100M100SF2RM Datasheet, PDF (1438/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Initialization/Application Information
49.5.3 Baud Rate Settings
The following table shows the baud rate that is generated based on the combination of the
baud rate prescaler PBR and the baud rate scaler BR in the CTAR registers. The values
calculated assume a 100 MHz system frequency and the double baud rate DBR bit is
clear.
NOTE
The clock frequency mentioned above is given as an example in
this chapter. Refer to the clocking chapter for the frequency
used to drive this module in the device.
Table 49-113. Baud Rate Values (bps)
2
4
6
8
16
32
64
128
256
512
1024
2048
4096
8192
16384
32768
2
25.0M
12.5M
8.33M
6.25M
3.12M
1.56M
781k
391k
195k
97.7k
48.8k
24.4k
12.2k
6.10k
3.05k
1.53k
3
16.7M
8.33M
5.56M
4.17M
2.08M
1.04M
521k
260k
130k
65.1k
32.6k
16.3k
8.14k
4.07k
2.04k
1.02k
Baud Rate Divider Prescaler Values
5
7
10.0M
7.14M
5.00M
3.57M
3.33M
2.38M
2.50M
1.79M
1.25M
893k
625k
446k
312k
223k
156k
112k
78.1k
55.8k
39.1k
27.9k
19.5k
14.0k
9.77k
6.98k
4.88k
3.49k
2.44k
1.74k
1.22k
872
610
436
49.5.4 Delay Settings
The following table shows the values for the Delay after Transfer (t_DT) and CS to SCK
Delay (T_CSC) that can be generated based on the prescaler values and the scaler values set
in the CTAR registers. The values calculated assume a 100 MHz system frequency.
1438
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.