K60P100M100SF2RM Datasheet, PDF (183/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Clock name
Ethernet IEEE 1588
clock
TRACE clock
Chapter 5 Clock Distribution
Table 5-1. Clock Summary (continued)
Run mode
clock frequency
Up to 100 MHz
Up to 100 MHz
VLPR mode
clock frequency
N/A
Up to 2 MHz
Clock source
System clock,
OSCERCLK,
MCGPLLCLK/
MCGFLLCLK, or
ENET_1588_CLKIN
System clock or
MCGOUTCLK
Clock is disabled
when…
Ethernet is disabled
Trace is disabled
5.5 Internal clocking requirements
The clock dividers are programmed via the SIM module’s CLKDIV registers. Each
divider is programmable from a divide-by-1 through divide-by-16 setting. The following
requirements must be met when configuring the clocks for this device:
1. The core and system clock frequencies must be 100 MHz or slower.
2. The bus clock frequency must be programmed to 50 MHz or less and an integer
divide of the core clock.
3. The flash clock frequency must be programmed to 25 MHz or less and an integer
divide of the bus clock.
4. The FlexBus clock frequency must be programmed to be less than or equal to the bus
clock frequency.
The following are a few of the more common clock configurations for this device:
Option 1:
Clock
Core clock
System clock
Bus clock
FlexBus clock
Flash clock
Frequency
50 MHz
50 MHz
50 MHz
50 MHz
25 MHz
Option 2:
Clock
Core clock
Frequency
100 MHz
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
183