K60P100M100SF2RM Datasheet, PDF (1496/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and registers
UARTx_S1 field descriptions (continued)
Field
0
PF
0 No framing error detected.
1 Framing error.
Parity Error Flag
Description
PF is set when PE is set, S2[LBKDE] is disabled, and the parity of the received data does not match its
parity bit. The PF is not set in the case of an overrun condition. When the PF bit is set it only indicates that
a dataword was received with parity error since the last time it was cleared. There is no guarantee that the
first dataword read from the receive buffer has a parity error or that there is only one dataword in the
buffer that was received with a parity error unless the receive buffer was a depth of one. To clear PF, read
S1 and then read the UART data register (D). Within the receive buffer structure the received dataword is
tagged if it was received with a parity error. That information is available by reading the ED register prior
to reading the D register.
0 No parity error has been detected since the last time this flag was cleared. If the receive buffer has a
depth greater than 1 then there may be data in the receive buffer what was received with a parity
error.
1 At least one dataword was received with a parity error since the last time this flag was cleared.
51.3.6 UART Status Register 2 (UARTx_S2)
The S2 register provides inputs to the MCU for generation of UART interrupts or DMA
requests. Also, this register can be polled by the MCU to check the status of these bits.
This register can be read or written at any time, with the exception of the MSBF and
RXINV bits which should only be changed by the user between transmit and receive
packets.
Addresses: UART0_S2 is 4006_A000h base + 5h offset = 4006_A005h
UART1_S2 is 4006_B000h base + 5h offset = 4006_B005h
UART2_S2 is 4006_C000h base + 5h offset = 4006_C005h
UART3_S2 is 4006_D000h base + 5h offset = 4006_D005h
UART4_S2 is 400E_A000h base + 5h offset = 400E_A005h
Bit
Read
Write
Reset
7
LBKDIF
0
6
RXEDGIF
0
5
MSBF
0
4
RXINV
0
3
RWUID
0
2
BRK13
0
1
LBKDE
0
0
RAF
0
UARTx_S2 field descriptions
Field
7
LBKDIF
LIN Break Detect Interrupt Flag
Description
LBKDIF is set when LBKDE is set and a LIN break character is detected, when 11 consecutive logic 0s (if
C1[M] = 0) or 12 consecutive logic 0s (if C1[M] = 1) appear on the receiver input. LBKDIF is set right after
receiving the last LIN break character bit. LBKDIF is cleared by writing a 1 to it.
Table continues on the next page...
1496
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.