K60P100M100SF2RM Datasheet, PDF (1601/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 52 Secured digital host controller (SDHC)
52.4.14 Interrupt Status Enable Register (SDHC_IRQSTATEN)
Setting the bits in this register to 1 enables the corresponding interrupt status to be set by
the specified event. If any bit is cleared, the corresponding interrupt status bit is also
cleared (i.e. when the bit in this register is cleared, the corresponding bit in interrupt
status register is always 0).
NOTE
• Depending on PROCTL[IABG] bit setting, SDHC may be
programmed to sample the card interrupt signal during the
interrupt period and hold its value in the flip-flop. There
will be some delays on the card interrupt, asserted from the
card, to the time the host system is informed.
• To detect a CMD line conflict, the host driver must set both
IRQSTATEN[CTOESEN] and IRQSTATEN[CCESEN] to
1.
Address: SDHC_IRQSTATEN is 400B_1000h base + 34h offset = 400B_1034h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
W
Reset 0
0
0
1
0
0
0
1
0
1
1
1
1
1
1
1
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
W
Reset 0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
1
SDHC_IRQSTATEN field descriptions
Field
31–29
Reserved
28
DMAESEN
27–25
Reserved
Description
This read-only field is reserved and always has the value zero.
DMA Error Status Enable
0b Masked
1b Enabled
This read-only field is reserved and always has the value zero.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1601