K60P100M100SF2RM Datasheet, PDF (1473/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 50 Inter-Integrated Circuit (I2C)
Clear IICIF
Y
Tx
Rx
Tx/Rx?
Last byte
Y
transmitted?
N
N
RXAK=0?
Y
Y
End of
address cycle
(master Rx)?
N
Last byte
Y
to be read?
N
Y
2nd to
last byte to be
read?
N
Master
N
mode?
Clear ARBL
Y
Arbitration
lost?
N
N
Y
(read)
Y
IIAAS=1?
Y
Address transfer
see note 1
SRW=1?
IIAAS=1?
N
Data transfer
see note 2
Rx
Tx/Rx?
N (write)
Tx
Write next
byte to Data reg
Set TXACK
Generate stop
signal (MST=0)
Set TX mode
Write data
to Data reg
Y
Transmit
next byte
ACK from
receiver?
N
Read data from
Data reg
and store
Switch to
Rx mode
Set Rx mode
Switch to
Rx mode
Dummy read
from Data reg
Generate stop
signal (MST=0)
Read data from
Data reg
and store
Dummy read
from Data reg
Dummy read
from Data reg
RTI
Notes:
1. If general call is enabled, check to determine if the received address is a general call address (0x00).
If the received address is a general call address, the general call must be handled by user software.
2. When 10-bit addressing addresses a slave, the slave sees an interrupt following the first byte of the extended address.
Ensure that for this interrupt, the contents of the Data register are ignored and not treated as a valid data transfer.
Figure 50-42. Typical I2C Interrupt Routine
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1473