K60P100M100SF2RM Datasheet, PDF (415/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
2
SP7
1
WP7
0
TP7
Chapter 19 Peripheral Bridge (AIPS-Lite)
AIPSx_PACRn field descriptions (continued)
Supervisor protect
Description
Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates .
0 This peripheral does not require supervisor privilege level for accesses.
1 This peripheral requires supervisor privilege level for accesses.
Write protect
Determines whether the peripheral allows write accesss. When this bit is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0 This peripheral allows write accesses.
1 This peripheral is write protected.
Trusted protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0 Accesses from an untrusted master are allowed.
1 Accesses from an untrusted master are not allowed.
19.3 Functional Description
The peripheral bridge serves as an interface between the crossbar switch and the slave
peripheral bus. It functions as a protocol translator.
Accesses which fall within the address space of the peripheral bridge are decoded to
provide individual module selects for peripheral devices on the slave bus interface.
19.3.1 Access support
Aligned and misaligned 32-bit and 16-bit accesses, as well as byte accesses are supported
for 32-bit peripherals. Misaligned accesses are supported to allow memory to be placed
on the slave peripheral bus. Peripheral registers must not be misaligned, although no
explicit checking is performed by the peripheral bridge. All accesses are performed with
a single transfer.
All accesses to the peripheral slots must be sized less than or equal to the designated
peripheral slot size. If an access is attempted which is larger (in size) than the targeted
port, an error response is generated.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
415