K60P100M100SF2RM Datasheet, PDF (1071/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

40.4.2 Interrupts
Chapter 40 Periodic Interrupt Timer (PIT)
All of the timers support interrupt generation. Refer to the MCU specification for related
vector addresses and priorities.
Timer interrupts can be enabled by setting the TIE bits. The timer interrupt flags (TIF)
are set to 1 when a timeout occurs on the associated timer, and are cleared to 0 by writing
a 1 to that TIF bit.
40.5 Initialization and Application Information
In the example configuration:
• The PIT clock has a frequency of 50 MHz.
• Timer 1 creates an interrupt every 5.12 ms.
• Timer 3 creates a trigger event every 30 ms.
First the PIT module must be activated by writing a 0 to the MDIS bit in the MCR.
The 50 MHz clock frequency equates to a clock period of 20 ns. Timer 1 needs to trigger
every 5.12 ms/20 ns = 256000 cycles and timer 3 every 30 ms/20 ns = 1500000 cycles.
The value for the LDVAL register trigger is calculated as:
LDVAL trigger = (period / clock period) -1
This means LDVAL1 should be written with 0x0003E7FF, and LDVAL3 should be
written with 0x0016E35F.
The interrupt for Timer 1 is enabled by setting TIE in the TCTRL1 register. The timer is
started by writing 1 to bit TEN in the TCTRL1 register.
Timer 3 shall be used only for triggering. Therefore Timer 3 is started by writing a 1 to
bit TEN in the TCTRL3 register, bit TIE stays at 0.
The following example code matches the described setup:
// turn on PIT
PIT_MCR = 0x00;
// Timer 1
PIT_LDVAL1 = 0x0003E7FF; // setup timer 1 for 256000 cycles
PIT_TCTRL1 = TIE; // enable Timer 1 interrupts
PIT_TCTRL1 |= TEN; // start Timer 1
// Timer 3
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1071