K60P100M100SF2RM Datasheet, PDF (260/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
PORT memory map (continued)
Absolute
address
(hex)
Register name
4004_D0A0 Interrupt Status Flag Register (PORTE_ISFR)
4004_D0C0 Digital Filter Enable Register (PORTE_DFER)
4004_D0C4 Digital Filter Clock Register (PORTE_DFCR)
4004_D0C8 Digital Filter Width Register (PORTE_DFWR)
Width
(in bits)
Access
Reset value
Section/
page
32
w1c 0000_0000h 11.4.4/263
32
R/W 0000_0000h 11.4.5/264
32
R/W 0000_0000h 11.4.6/265
32
R/W 0000_0000h 11.4.7/265
11.4.1 Pin Control Register n (PORTx_PCRn)
For PCR1 to PCR5 of the port A, bit 0, 1, 6, 8, 9,10 reset to 1; for the PCR0 of the port
A, bit 1, 6, 8, 9, 10 reset to 1; in other conditions, all bits reset to 0.
Addresses: 4004_9000h base + 0h offset + (4d × n), where n = 0d to 31d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
0
IRQC
W
w1c
0
0
0
MUX
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PORTx_PCRn field descriptions
Field
31–25
Reserved
24
ISF
Description
This read-only field is reserved and always has the value zero.
Interrupt Status Flag
The pin interrupt configuration is valid in all digital pin muxing modes.
23–20
Reserved
19–16
IRQC
0 Configured interrupt has not been detected.
1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the
corresponding flag will be cleared automatically at the completion of the requested DMA transfer,
otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive
interrupt that remains asserted then flag will set again immediately.
This read-only field is reserved and always has the value zero.
Interrupt Configuration
The pin interrupt configuration is valid in all digital pin muxing modes. The corresponding pin is configured
to generate interrupt / DMA Request as follows:
0000
0001
0010
0011
0100
1000
Interrupt/DMA Request disabled.
DMA Request on rising edge.
DMA Request on falling edge.
DMA Request on either edge.
Reserved.
Interrupt when logic zero.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
260
Freescale Semiconductor, Inc.